Metal-oxide Semiconductor (MOS) transistors of semiconductor memory devices typically include a gate pattern formed on a substrate and source/drain regions formed in the substrate at opposite sides of the gate pattern. Generally, the source/drain regions are in a lightly doped structure that suppresses hot carrier effects and may provide for a high level of integration of the circuit. Conventionally, the source/drain regions are electrically connected to an upper conductive layer that fills a contact hole formed in an interlayer insulation layer.
As semiconductor devices become more highly integrated within a circuit, the area of the source/drain regions and the contact hole may become reduced. Thus, self-aligned contact hole technologies and borderless contact technologies have been proposed.
FIGS. 1 and 2 are cross-sectional views showing a method of forming a conventional semiconductor device.
Referring to FIG. 1, a device isolation layer (not shown) is formed in a substrate 1 to define an active region and then gate patterns 5 are formed to cross over the active regions in parallel. The gate pattern 5 includes a gate insulation layer 2, a gate electrode 3, and a hard mask layer 4 that are sequentially stacked. Conventionally, the gate insulation layer 2 is formed of thermal oxide and the gate electrode 3 is formed of a double-layered structure of polysilicon and tungsten silicide that are sequentially stacked. The hard mask layer 4 is formed of silicon nitride.
Using the gate pattern 5 as a mask, impurity ions are implanted to form lightly doped impurity diffusion layers 7a in the active region at both sides of the gate pattern 5. Spacers 8 are formed on both sidewalls of the gate pattern 5. The spacers 8 are formed of silicon nitride. Using the gate pattern 5 and the spacers 8 as a mask, impurity ions are implanted into the active region to form a heavily doped impurity diffusion layer 7b. The lightly and heavily doped impurity diffusion layers 7a and 7b form a lightly doped drain structure (LDD structure).
A conformal etch stop layer 9 is formed on a surface of the substrate 1 with the heavily doped impurity diffusion layer 7b. An interlayer insulation layer 10 is formed on the etch stop layer 9 to fill a gap region between the gate patterns 5. The etch stop layer 9 is formed of silicon nitride and the interlayer insulation layer 10 is formed of silicon oxide. The etch stop layer 9 may be provided to form a borderless contact hole (not shown) that exposes the active region and the device isolation layer. That is, the device isolation layer exposed during formation of the borderless contact hole is protected by the etch stop layer 9. In this case, the bottom width of the gap region between the gate patterns 5 is decreased by the etch stop layer 9. As a result, a void C may occur in the gap region while the interlayer insulation layer 10 is formed.
Referring to FIG. 2, a photoresist pattern (not shown) is formed on the interlayer insulation layer 10 to define a contact hole 11. Then, using the photoresist pattern as a mask, the interlayer insulation layer 10 is etched to expose the etch stop layer 9. The exposed etch stop layer 9 is located on the heavily doped impurity diffusion layer 7b and the spacers 8. The exposed etch stop layer 9 is removed to form the contact hole 11 that exposes the heavily doped impurity diffusion layer 7b. The contact hole 11 is a self-aligned contact hole that aligns itself to the hard mask layer 4 and the spacers 8. In addition, the contact hole 11 is a borderless contact hole that exposes a predetermined region of the device isolation layer (not shown). A conductive pattern 12 is formed to fill the contact hole 11.
According to the prior art discussed above, the etch stop layer 9 and the spacer 8 are formed of identical insulation material. Thus, when the exposed etch stop layer 9 is removed so as to form the contact hole 11, over etching and curved sidewalls of the spacers 8 may cause reduction of a bottom width of the spacers 8. As a result, the lightly doped impurity diffusion layers 7a may be exposed at regions d thereof.
As is further illustrated in FIGS. 1 and 2, each of the lightly doped impurity diffusion layers 7a is thinner than the heavily doped impurity diffusion layer 7b in junction depth. Therefore, when power is supplied to the conductive pattern 12, leakage current may flow through the exposed regions d of the lightly doped impurity diffusion layers into the substrate 1. That is, a leakage current characteristic of a device may be degraded. In the case where the exposed regions d of the lightly doped impurity diffusion layers are over etched and suffer from etching damage, the leakage current characteristic may be further deteriorated.
The leakage current characteristic may be further degraded if the contact hole 11 is formed as a butting contact hole (not shown). The butting contact hole exposes a portion of a gate electrode in the gate pattern and an impurity diffusion layer. In this case, the hard mask layer 3 in the gate pattern 5 is also etched, such that the spacer 8 may be further over etched. Thus, the above leakage current problems may be exacerbated.